Progressive Training Strategies for Routability Prediction in Modern Floorplanning

Abstract

Modern integrated circuit design faces increasing challenges in achieving design  closure due to complex routing congestion patterns that emerge during physical implementation.  This paper presents a progressive training framework for routability prediction that decomposes the learning task into hierarchical stages aligned with the natural abstraction levels of physical  design. The proposed methodology employs a three-stage architecture that progressively refines  predictions from coarse-grained global congestion estimation through intermediate pin accessibility analysis to fine-grained design rule violation detection. By leveraging convolutional  neural networks for spatial feature extraction and graph neural networks for topological  modeling, our approach achieves superior prediction accuracy compared to conventional single stage methods. Experimental validation on industry-standard benchmarks demonstrates an area  under the curve exceeding 0.92, representing a 7% improvement over baseline approaches, while  maintaining inference latency below 100 milliseconds suitable for interactive placement optimization workflows.